Rambus Inc., a leading provider of chip-to-chip interface products and services, along with Toshiba and Elpida, today announced XDR? DRAM. XDR DRAM uses Rambus' XDR memory interface technology, formerly code-named Yellowstone. Running at 3.2GHz, XDR DRAM offers 8x the bandwidth of today's best-in-class PC memory. As Rambus announced earlier this year, Sony Corporation and Sony Computer Entertainment Inc. have licensed the XDR memory interface for utilization in future broadband applications with "Cell." The XDR DRAM family has been architected to offer mainstream memory solutions for a broad range of applications. XDR DRAM is expected to initially serve the high-bandwidth needs of consumer, graphics, and networking applications, with eventual applicability for PC main memory, server and mobile systems when these applications require higher levels of bandwidth. XDR DRAM can provide the cost benefits of mainstream memory while still outperforming low-volume specialty DRAMs. XDR DRAM offers significant cost savings by providing the same system bandwidth as alternatives with fewer DRAM components, low-cost 4-layer PCBs, and inexpensive industry-standard packages. Initially XDR DRAM will be offered at 3.2GHz with a roadmap to 6.4GHz and beyond, enabling memory system bandwidths up to 100GB/s. XDR DRAM will be available in multiple speed bins, device densities, and device widths. With densities ranging from 256Mb to 8Gb, and device widths ranging from x1 to x32, XDR DRAM satisfies the needs of both high-bandwidth and high-capacity systems. XDR memory's novel matrix topology allows point-to-point differential data interconnects to scale to multi-GHz speeds, while the bussed address and command signals allow a scalable range of memory system capacity supporting from one to 36 DRAM devices. The Rambus XDR DRAM memory system solution achieves an order of magnitude higher performance than today's standard memories while utilizing the fewest ICs. A single, 2-byte wide, 3.2 GHz XDR DRAM component provides up to 6.4 GB/sec bandwidth over the XDR Interconnect. The XDR interface uses a small number of very high-speed signals to carry all address, data, and control information between CPU, NPU or ASIC controller and the DRAM components. The XDR solution was engineered to be effective in small high-bandwidth consumer systems as well as in high-performance main memory applications. This interface standard is implemented on standard CMOS DRAM memory cores and CMOS CPU or controller chips for applications such as high-performance main memory, PC graphics, game consoles, high-performance networking systems, and other demanding applications requiring high bandwidths from a memory component. The XDR memory solution provides a total system solution to many of the complex issues and problems that engineers face in designing cost effective, high-performance memory subsystems. The XDR infrastructure, such as DRAM models, controller IO cells, clock generators, data sheets and system design guides, are available today for semiconductor and system design. From chip design to system integration and volume production, Rambus provides comprehensive services, support and a single point of contact for the entire memory system design to guarantee compatibility across multiple DRAM component vendors. Toshiba and Elpida expect to begin shipping XDR DRAM in 2004, ramping to volume production in 2005. XDR DRAM Technology Summary - 1.8MB PDF XDR DRAM System Design Overview - 3.7MB PDF Related Story: Restarting The Memory War: Rambus XDR DRAM Tech Preview @ GamePC