Intel announces the shipping clock speed for its Core 2 Extreme and the top Core 2 Duo CPUs. They also give a sneak peek into the roadmap and give us some hands-on benchmarking time.
Intel's new Core 2 CPUs are probably the most anticipated processors yet to ship since AMD's first Athlon 64. In many ways, Intel's new desktop CPUs, set to launch in July, are the most important CPU products for the company since the original P6 processor in 1995. Intel has been promising lower power utilization and greater performance.
We've described the Core 2 architecture back in March. The Core 2 microarchitecture gives us some clues as to why performance might be better. Conroe is a four-wide architecture, so can issue four instructions per clock, as opposed to the three-wide used in NetBurst and Athlon 64 architectures. The Core 2 will also contain a full 128-bit wide SSE (Streaming SIMD (single instruction, multiple data) Extensions) engine that can execute one SIMD instruction per clock. The Extreme and higher-end mainstream desktop CPUs will offer 4MB of shared L2 cache. Finally, the use of micro-ops and macro-ops fusion, which can combine certain types of instructions as they come into the pipeline, enhances performance.
But the architecture has a much shorter pipeline than the current Pentium D's?14 versus 31 stages. That suggests that overall clock frequencies will be lower. Can the new features overcome the clock rate disparities? We'll take a look at that in a moment. However, let's take a look at what Intel plans to ship this year.
ExtremeTech
We've described the Core 2 architecture back in March. The Core 2 microarchitecture gives us some clues as to why performance might be better. Conroe is a four-wide architecture, so can issue four instructions per clock, as opposed to the three-wide used in NetBurst and Athlon 64 architectures. The Core 2 will also contain a full 128-bit wide SSE (Streaming SIMD (single instruction, multiple data) Extensions) engine that can execute one SIMD instruction per clock. The Extreme and higher-end mainstream desktop CPUs will offer 4MB of shared L2 cache. Finally, the use of micro-ops and macro-ops fusion, which can combine certain types of instructions as they come into the pipeline, enhances performance.
But the architecture has a much shorter pipeline than the current Pentium D's?14 versus 31 stages. That suggests that overall clock frequencies will be lower. Can the new features overcome the clock rate disparities? We'll take a look at that in a moment. However, let's take a look at what Intel plans to ship this year.
ExtremeTech
