Juts spotted this at Digit-life.com:
Despite the launch of new server Opteron CPU series with new 64-bit x86-64 architecture is scheduled for tomorrow by AMD, the Web already offers comprehensive information about them, so we couldn?t fail to make use of it. Perhaps, tomorrow will bring some more specs or architectural details, but such a major event needs additions anyway.
Opteron chips introduce several key features: 64-bit core, 64Kb associative duplex instruction cache + 64Kb associative duplex data cache (L1); 1Mb 16-channel L2 cache; integrated DDR controller supporting DDR200 and DDR266 SDRAM; HyperTransport module supporting up to 3 buses with 19.2Gbps total throughput.
Despite the launch of new server Opteron CPU series with new 64-bit x86-64 architecture is scheduled for tomorrow by AMD, the Web already offers comprehensive information about them, so we couldn?t fail to make use of it. Perhaps, tomorrow will bring some more specs or architectural details, but such a major event needs additions anyway.
Opteron chips introduce several key features: 64-bit core, 64Kb associative duplex instruction cache + 64Kb associative duplex data cache (L1); 1Mb 16-channel L2 cache; integrated DDR controller supporting DDR200 and DDR266 SDRAM; HyperTransport module supporting up to 3 buses with 19.2Gbps total throughput.
